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constant - frequency, current - mode step - up dc/dc controller data sheet ad p1621 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their re spective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2006 C 2012 analog devices, inc. all rights rese rved. features 92% efficiency (no sense resistor required) 1.0% initial accuracy ic supply voltage range: 2.9 v to 5.5 v power - input voltage as low as 1.0 v capable of high supply input voltage (>5.5 v) with an external npn or a resistor v in uvlo and 35 ma shu nt regulator external slope compensation with 1 resistor programmable operating frequency (100 khz to 1.5 mhz) with 1 resistor lossless current sensing for switch - node voltage <30 v resistor current sensing for switch - node voltage >30 v synchronizable to external clock current - mode operation for excellent line and load transient responses 10 a shutdown current current limit and thermal overload protection soft start in 2048 clock cycles supported by adisim power ? design tool applications apd bias portable electronic equipment isolated dc/dc converter step - up/step - down dc/dc converter led driver for laptop computer and navigation system lcd backlighting general description the adp1621 is a fixed - frequency, p ulse - width modulation (pwm), current - mode, step - up converter controller. it drives an external n - channel mosfet to convert the input voltage to a higher output voltage. the adp1621 can also be used to drive flyback, sepic, and forward converter topologies, either isolated or nonisolated. the adp1621 eliminates the use of a current - sense power resistor by measuring the voltage drop across the on resistance of the n - channel mosfet. this technique, allowed up to a maximum voltage of 30 v at the switch node, m aximizes efficiency and reduces cost. for switch - node voltages higher than 30 v or for more accurate current limiting, the cs pin can be connected to a current - sense resistor in the source of the mosfet. the slope compensation is implemented by an external resistor, allowing a wide range of external components (inductors and mosfets), and can be chosen for various switching frequencies and input and output voltages. typical application circuit adp1621 in gate pgnd agnd fb sdsn comp freq gnd pin cs r1 35.7k? 1% r2 11.5k? 1% c1 47f 6.3v l1 4.7h m1 c comp 1.8nf c out1 1f 10v f osc = 600khz c1 = murata grm31cr60j476m c out3 = sanyo poscap 6tpe150m l1 = toko fdv0630-4r7m m1 = vishay si7882dp d1 = vishay ssa33l r s 80? c out2 10f 10v r freq 31.6k? 1% c out3 150f 6.3v 2 v out = 5v 1a v in = 3.3v d1 c3 1f 10v c4 0.1f 10v c2 120pf r comp 9.09k? 06090-001 figure 1 . high efficiency output boos t converter in lossless mode, 3.3 v input, 5 v output (bootstrapped) 100 30 0.01 10 load current (a) efficiency (%) 90 80 70 60 50 40 0.1 1 06090-042 figure 2 . efficiency of circuit shown in figure 1 the adp1621 supply input voltage range is 2.9 v to 5.5 v, although higher input v oltages are possible with the use of a small - signal npn pass tran sistor or a single resistor. the voltage of the power input can be as low as 1 v for fuel cell applications. the switching frequency is set by an external resistor over a range of 100 khz to 1.5 mhz and can be synchronized to an external clock by using the sdsn pin. the shutdown quiescent current is less than 10 a. the adp1621 has a thermal shutdown feature that shuts down the gate driver when the junction temperature reaches approximately 15 0c . the internal soft start circuit limits inrush current at startup. the adp1621 is available in the 10 - lead msop lead - free package and is specified over the ?40c to +125c junction tempe rature range .
adp1621 data sheet rev. b | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 typical application circuit ............................................................. 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 absolute maximum ratings ............................................................ 5 thermal resistance ...................................................................... 5 esd caution .................................................................................. 5 simplified block diagram ............................................................... 6 pin configuration and function descriptions ............................. 7 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 12 control loop ............................................................................... 12 current-sense configurations .................................................. 12 current limit .............................................................................. 13 undervoltage lockout ............................................................... 13 shutdown ..................................................................................... 13 soft start ...................................................................................... 13 internal shunt regulators .......................................................... 13 setting the oscillator frequency and synchronization frequency .................................................................................... 13 application information: boost converter ................................. 14 adisimpower design tool ....................................................... 14 duty cycle ................................................................................... 14 setting the output voltage ........................................................ 14 inductor current ripple ............................................................ 14 inductor selection ...................................................................... 14 input capacitor selection .......................................................... 15 output capacitor selection ....................................................... 15 diode selection ........................................................................... 15 mosfet selection ..................................................................... 16 loop compensation .................................................................. 16 slope compensation .................................................................. 17 current limit .............................................................................. 18 light load operation ................................................................ 18 recommended component manufacturers ........................... 19 layout considerations ................................................................... 20 efficiency considerations ............................................................. 21 examples of application circuits ................................................. 22 standard boost converterdesign example ........................ 22 bootstrapped boost converter ................................................. 23 sepic converter circuit ........................................................... 27 low voltage power-input circuit ............................................ 27 led driver application circuits ............................................. 28 related parts .................................................................................... 30 outline dimensions ....................................................................... 31 ordering guide .......................................................................... 31 revision history 6/12rev. a to rev. b change to features section ............................................................. 1 added adisimpower design tool section ................................. 14 change to table 6 ........................................................................... 30 updated outline dimensions ....................................................... 31 changes to ordering guide .......................................................... 31 12/06rev. 0 to rev. a changes to table 1 ............................................................................ 3 changes to table 2 ............................................................................ 5 added table 3 .................................................................................... 5 changes to table 5 .......................................................................... 19 changes to ordering guide .......................................................... 31 7/06revision 0: initial version
data sheet adp1621 rev. b | page 3 of 32 specifications v in = 5 v, r freq = 100 k?, f osc = 200 k hz, t j = ?40c to 125c, unle ss otherwise noted. table 1 . parameter symbol conditions min typ max unit main control loop internal soft start time t ss 2048 cycles pin supply voltage 1 v pin 2.9 v s hunt v in supply voltage 1 v in 2.9 v shunt v shunt regulation voltage v shunt i in = 3 ma, i pin = 3 ma, t a = 25c 5.4 5.6 5.7 v i in = 3 ma, i pin = 3 ma 5.2 5.6 6.0 v shunt resistance r shunt current into in = 8 ma to 1 2 ma 13 ? current into pin = 8 ma to 12 ma 7 ? in quiescent current i in v in = 2.9 v to 5.5 v, v fb = 1.215 v 1.8 3 ma in shutdown current v in = 2.9 v to 5.5 v, sdsn = gnd 1 10 a pin supply current i pin static mode, no switching v fb = 1.3 v, v com p < v c o m p, z c t , gate = 0 v 1 10 a shutdown mode sdsn = gnd 1 10 a undervoltage lockout threshold at in pin v uvlo v uvlo rising 2.2 2.5 2.8 v v uvlo hysteresis ?80 mv fb regulation voltage v fb t a = 25c 1.203 1.215 1.227 v 1.197 1.215 1.233 v fb input current i fb v fb = 1.215 v, t a = 25c ?75 +25 +75 na line regulation 2 ?v fb /?v in 2.9 v v in 5 v, t j = ?40c to + 85c 0.02 0.06 %/v 2.9 v v in 5 v, t j = ?40c to + 125c 0.02 0.072 %/v load regulation 3 ?v fb /?v comp v comp = 1.4 v to 1. 5 v ?1 ?0.1 % error amplifier transconductance g m 300 s comp zero - current threshold v c o m p, z c t 0.85 1.0 1.15 v comp clamp high voltage v comp,clamp t j = ?40c to + 85c 1.9 2.0 2.1 v t j = ?40c to + 125c 1.9 2.0 2.2 v current - sense amplifier gain n 7.5 9.5 11.5 v/v peak slope - compensation current at cs pin 4 i sc,pk v cs = 0 v to 100 mv maximum across r s (gate high) 55 70 85 a cs pin leakage current i cs,leak v cs = 30 v (gate low) 5 a shutdown time t sd sdsn pin from high to low or left floati ng 50 s thermal shutdown threshold 5 t tmsd 150 c thermal shutdown hysteresis 5 ?10 c oscillator oscillator frequency range 6 f osc 100 1500 khz oscillator frequency f osc r freq = 65 k?, t a = 25c 255 325 395 khz oscillator frequency tempco f osc,tc 0.06 %/c sdsn input level threshold v sdsn,thresh v in = v pin = 5 v 1.5 1.7 1.9 v sdsn threshold hysteresis ?0.19 v sdsn internal pull - down resistor r sdsn 100 k? synchronization minimum pulse width t sync,min v sdsn = 0 v to v in 45 100 ns synchronization maximum pulse width t sync,max v sdsn = 0 v to v in 0.8/f sync ns synchronization frequency f sync 110 1800 khz gate minimum on time t on,min v fb = 1.215 v, v comp = 1.0 v 180 215 ns gate minimum off time t off,min v fb = 1.215 v, v comp = 2.0 v 190 230 ns maximum duty cycle 6 , 7 d max f sw = 200 khz, r freq = 100 k ? 93 97 % recommended maximum synchronized frequency ratio 6 , 8 f sync /f osc f osc = 200 khz, r freq = 100 k?, f sync = f sw 1.1 1.2 1.4
adp1621 data sheet rev. b | page 4 of 32 parameter symbol conditions min typ max unit gate driver gate rise time 9 t r c gate = 3.3 nf 17 ns gate fall time 9 t f c gate = 3.3 nf 13 ns 1 the maximum input voltage is the shunt regulation voltage, which is typically 5.5 v and can range from 5.3 v to 6.0 v over th e specified temperature range. 2 the adp1621 is tested in a feedback servo lo op, which servos v fb to the internal reference voltage. the voltage change in fb is measured while v in is changed from 2.9 v to 5 v. the l ine regulation is calculated by (?v fb /v fb ) 100%/?v in . 3 the adp1621 is tested in a feedback servo loop, which servos v fb to the internal reference voltage, and v comp is forced from 1.4 v to 1.5 v. the v comp range is (1.0 v v comp 2. 0 v). 4 the peak s lope - compensation current at the cs pin is typically 70 a, and effectively clamped at 1 16 mv. thus, r s should not exceed 1. 6 k? (1 16 mv/70 a). 5 guaranteed by design for thermal shutdown. when the thermal junction temperature of the adp1621 reaches appro ximately 150c, the adp1621 goes into thermal shutdown and the ga te voltage is pulled low. when the junction temperature drops below about 140c, the soft start sequence is initiated and the adp1621 resumes normal operation. 6 f osc is the natural oscillati on frequency, f sync is the synchronization frequency, and f sw is the switching frequency. if synchronization is used, then f sw = f sync ; otherwise, f sw = f osc . 7 guaranteed by design and bench characterization. 8 to ensure proper synchronization operation, set the synchronization freque ncy, f sync , to 1.2 of the free - running frequency, f osc . although the switching frequency can be synchronized to as high as 1.8 mhz, the peak slope - compensation current decreases at higher synchronization frequencies. it is re commended that the maximum f sync be less than 1.4 of f osc and should not exceed 1.8 mhz. the slope - compensation resistor , r s , should be chosen for the synchronization frequency (see the slope compensation section in the application information: boost converter section ). 9 g ate rise and fall times are measured from 10% to 90% levels.
data sheet adp1621 rev. b | page 5 of 32 absolute maximum rat ings table 2 . parameter rating in to gnd ?0.3 v to v shunt fb, comp, sdsn, freq, gate to gnd ?0.3 v to (v in + 0.3 v) cs to gnd ?5 v to +33 v pin to p gnd ?0.3 v to v shunt supply current into in 25 ma supply current into pin 35 ma storage temperature range ?55c to +150c junction operating temperature range 1 ?55c to +150c junction storage temperature range ?55c to +150c lead temperature (sold ering, 10 sec) 300c package power dissipation 1 (t j,max ? t a )/ ja 1 in applications where high power dissipation and poor package thermal resistance are present, the maximum ambient temperature may need to be derated. maximum ambient temperature (t a, max ) is dependent on the maximum operating junction temperature (t j, max = 150 o c), the maximum power dissipation of the device in the application (p d, max ), and the junction - to - ambient thermal resistance of the package in the application ( ja ), is given by the f ollowing equation: t a, max = t j, max - -- ( ja x p d, max ) . stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions abov e those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings apply individually only, not in combination. unle ss otherwise specified, all other voltages are referenced to gnd. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 3 . thermal resistance package type ja unit 10- lead msop on a 2 - layer pcb 200 c/w 10- lead msop on a 4 - layer pcb 172 c/w junction - to - ambient thermal resistance of the package is based on modeling and c alculation using 2 - layer and 4 - layer boards, and natural convection. the junction - to - ambient thermal resistance is application - and board - layout dependent. in applications where high maximum power dissipation exists, attention to thermal dissipation issues in board design is required. esd caution
adp1621 data sheet rev. b | page 6 of 32 simplified block dia gram cs pgnd freq osc v osc 1.4v v ref 1.215v 5.5v 5.5v 100k? r s set slope comp pwm comparator adp1621 gate driver error amplifier gnd fb gate pin comp in sdsn g m n + + soft start (2048 cycles) uvlo 06090-002 figure 3 . adp1621 simplified block diagram
data sheet adp1621 rev. b | page 7 of 32 pin c onfiguration and fun ction descriptions sdsn 1 gnd 2 com p 3 fb 4 freq 5 in 10 cs 9 pin 8 ga te 7 pgnd 6 adp1621 t op view (not to scale) 06090-003 figure 4 . pin configuration table 4 . pin function descriptions pin o. nemonic description 1 sdsn shutdown and synchronization input. turn the adp1621 on by drivin g sdsn high; turn it off by driving sdsn low. if sdsn is left floating or when the sdsn is pulled low, the adp1621 goes into shutdown after 50 s. if synchronization is needed, synchronize the switching frequency to an external clock by connecting the exte rnal clock to the sdsn pin. an internal 100 k? pull - down resistor is connected from sdsn to gnd. 2 gnd ground. 3 comp regulation control compensation node. comp is the output of the internal transconductance error amplifier. connect a series rc from comp to gnd to compensate the regulator. the nominal voltage range for this pin is 1.0 v to 2.0 v. 4 fb feedback input. fb is the input to the internal transconductance error amplifier. drive fb from the output voltage through a resistive voltage divider. th e ratio of the voltage divider sets the output voltage. the regulation voltage at fb is nominally 1.215 v. 5 freq frequency control input. connect a resistor from freq to gnd to set the free - running switching frequency between 100 khz and 1.5 mhz. the no minal voltage of this pin is 1.4 v. 6 pgnd power ground input. pgnd is the ground return for the internal gate driver and the negative input of the internal current - sense amplifier. connect pgnd to gnd as close to the adp1621 as possible. 7 gate gate dri ver output. the maximum gate driver output is equal to the pin voltage. gate drives the gate of the external n - channel power mosfet. connect gate to the gate of the mosfet. 8 pin power input. pin powers the gate driver output. an internal 5.5 v shunt regu lator is connected to this pin. bypass pin to pgnd with a 0.1 f or greater capacitor. 9 cs current - sense input. cs is the positive input of the current - sense amplifier. when gate is turned on, the voltage at the cs pin increases linearly from 0 v to a m aximum of 116 mv, and the nominal peak slope - compensation output current is 70 a. when gate is off, the cs function is disabled. for current sensing in lossless mode, connect cs to the drain of the power mosfet. the absolute maximum voltage at cs is 33 v. for higher accuracy current sensing or higher switch - node voltages, connect cs to a current - sense power resistor in the source of the power mosfet. in both sensing methods, it is required to add a slope - compensation resistor, r s , to the cs pin to achieve stability in the inductor current for duty cycles greater than 50%. however, it is recommended to add r s for all duty cycles because load transients can momentarily cause the duty cycle to be greater than 50%, even when the steady - state duty cycle is less than 50%. 10 in input voltage. in powers the adp1621 internal circuitry. an internal 5.5 v shunt regulator is connected to this pin. bypass in to gnd with a 0.1 f or greater capacitor.
adp1621 data sheet rev. b | page 8 of 32 typical performance characteristics 100 30 0.01 10 load current (a) efficiency (%) 90 80 70 60 50 40 0.1 1 t a = 25c f sw = 220khz v in = 3.3v v out = 5v 06090-004 figure 5 . efficiency vs. load current ch1 20mv ch2 2v m2s a ch2 2.6v 1 2 t a = 25c v in = 3.3v v out = 5v load = 1a v out ripples @ 5v ac-coupled ch2 = gate 06090-005 figure 6 . output voltage ripple of the circuit shown in figure 1 1 . 2160 5 1 . 2157 5 2 . 5 6 . 0 v i n (v) v fb (v) t a = 25 c 1 . 2160 0 1 . 2159 5 1 . 2159 0 1 . 2158 5 1 . 2158 0 3 . 0 3 . 5 4 . 0 4 . 5 5 . 0 5 . 5 06090-006 figure 7. v fb vs. v in 92 84 100 switching frequency (khz) efficiency (%) 91 90 89 88 87 86 85 300 500 700 900 1100 1300 1500 t a = 25c v in = 3.3v v out = 5v load = 1a load = 0.5a 06090-007 figure 8 . effici ency vs. switching frequency 100 0.00001 0 7 supply voltage (v) supply current (ma) t a = 25c no switching 10 1 0.1 0.01 0.001 0.0001 1 2 3 4 5 6 i in i pin 06090-008 figure 9 . supply current vs. supply voltage 2.5 0 1.17 1.29 v fb (v) v comp (v) t a = 25c v in = 5v 2.0 1.5 1.0 0.5 1.19 1.21 1.23 1.25 1.27 06090-009 figure 10 . v comp vs. v fb
data sheet adp1621 rev. b | page 9 of 32 45 0 0 1800 switching frequency (khz) pin supply current (ma) mosfet q g = 25nc mosfet q g = 15nc mosfet q g = 7nc 40 35 30 25 20 15 10 5 200 400 600 800 1000 1200 1400 1600 06090-010 figure 11 . pin supply current vs. switching frequency 2.60 2.40 ?50 150 temperature (c) v uvlo (v) sdsn = 5v 2.55 2.50 2.45 0 50 100 06090-011 figure 12 . v uvlo threshold vs. temperature 1.03 0.97 ?50 150 temperature (c) normalized frequency ( f osc / f osc,25c ) 0 50 100 1.02 1.01 1.00 0.99 0.98 v in = 5v 06090-012 figure 13 . frequency vs. temperature 35 0 0 50 gate capacitance (nf) gate rise and fall times (ns) 30 25 20 15 10 5 5 10 15 20 25 30 35 40 45 t a = 25c v in = v pin = 5v t r or t f is from 10% to 90% of the gate voltage t f t r 06090-013 figure 14 . gate rise and fall times vs. c gate 1600 0 0 200 r freq (k ?) f osc (khz) 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 20 40 60 80 100 120 140 160 180 06090-014 figure 15 . oscillator frequ ency vs. resistance 198 191 2 v in (v) f osc (khz) 197 196 195 194 193 192 3 4 5 t a = 25c r freq = 100k ? 06090-015 figure 16 . oscillator frequency vs. v in
adp1621 data sheet rev. b | page 10 of 32 250 0 ?40 160 cs leakage (na) temperature (c) v in = 5v cs = 30v 200 150 100 50 10 60 110 06090-016 figure 17 . temperature vs. cs leakage 8 ?16 ?50 150 temperature (c) fb bias current (na) 4 0 ?4 ?8 ?12 0 50 100 v fb = 1.2113v at 25c fb bias current is measured by forcing a constant 1.2113v over the temperature range. 06090-017 figure 18 . fb bias current vs. temperature 90 0 1.0 f sync / f osc peak slope compensation current (a) 2.2 f osc = 200khz f osc = 550khz 80 70 60 50 40 30 20 10 1.2 1.4 1.6 1.8 2.0 06090-018 figure 19 . slope - compensation current vs. f sync /f osc 1.6 0 ?50 150 temperature (c) shutdown in current (a) 0 50 100 1.4 1.2 1.0 0.8 0.6 0.4 0.2 v in = 5v sdsn = 0v 06090-019 figure 20 . shutdown in current vs. temperature 1.2165 1.2120 ?50 150 temperature (c) v fb (v) 0 50 100 v in = 5v sdsn = 0v 1.2160 1.2155 1.2150 1.2145 1.2140 1.2135 1.2130 1.2125 06090-020 figure 21 . fb voltage vs. temperature ch1 5v ch2 5v ch4 500ma ? m2s a ch1 2.9v 1 2 4 t a = 25c v in = 3.3v v out = 5v load = 0.1a dcm operation ch1 = gate ch4 = inductor current ch2 = drain voltage 06090-021 figure 22 . dcm switching wave form
data sheet adp1621 rev. b | page 11 of 32 ch1 5v ch2 5v ch4 500ma? m2s a ch1 2.9v 1 2 4 t a = 25c v in = 3.3v v out = 5v load = 0.3a ccm operation ch1 = gate ch4 = inductor current ch2 = drain voltage 06090-022 figure 23 . ccm switching waveform ch1 1v ch3 5v ch2 5v m2ms a ch1 4.5v 1 2 3 t a = 25c v in = 3.3v v out = 5v f sw = 220khz soft-start = 9.3ms ch3 = gate ch1 = v out ch2 = sdsn 06090-023 figure 24 . soft start waveform ch1 50mv ch2 2v m400s a ch2 3.8v 2 1 t a = 25c v out = 5v load at v out = 1a ch1 = v out , ac-coupled ch2 = v in from 3v to 4v 06090-024 figure 25 . line transient response of the configuration shown in figur e 1 with a 1 a load ch1 50mv ch4 1a? m200s a ch4 700v 1 4 t a = 25c v in = 3.3v v out = 5v load current from 0.2a to 1.2a output, ac-coupled 06090-025 figure 26 . load transient response of the circuit shown in figure 1 ch1 50mv ch2 2v m400s a ch2 3.8v 2 1 t a = 25c v out = 5v no load at v out ch1 = v out , ac-coupled ch2 = v in from 3v to 4v 06090-026 figure 27 . line transient response of the configuration shown in figure 1 with no load
adp1621 data sheet rev. b | page 12 of 32 theory of operation the adp1621 is a fixed - frequency, current - mode, step - up dc/dc converter controller. it drives an external n - channel mosfet to step the input voltage up to a higher output voltage. it can be used for sepic, flyback, boost, buck - boost, forward, and other converter topologies. it operates at a fixed switching frequency that is set by an external resistor over a range of 100 khz to 1.5 mhz, and it can be synchronized to an external clock by connecting th e sdsn pin to the clock. the input supply current to the adp1621 is less than 3 ma during normal operation and less than 10 a during shutdown . the adp1621 can drive large external mosfets, allowing it to support load currents in excess of 10 a. control l oop the adp1621 uses a current - mode architecture to regulate the output voltage. the output voltage is monitored at fb through a resistive voltage divider. the voltage at fb is compared to the internal 1.215 v reference voltage by the internal transconduc tance error amplifier to create an error current at comp. a resistor - capacitor compensation impedance connected from comp to gnd converts the error current to an error voltage. at the beginning of the switching cycle, the mosfet is turned on and the induc tor current ramps up. the mosfet current is measured and converted to a voltage using r cs or r dson and is added to the stabilizing slope - compensation ramp. the resulting voltage sum passes through the current - sense amplifier to generate the current - sense v oltage. when the current - sense voltage is greater than the comp error voltage, the mosfet is turned off and the inductor current ramps down until the internal clock initiates the next switching cycle. the duty - cycle of the pwm modulator is thus adjusted to provide the necessary load current at the desired output voltage. because the output voltage ultimately controls the peak inductor current through the comp error voltage, this scheme is referred to as peak current - mode control. with light loads, the conve rter can also operate under discon - tinuous conduction mode and pulse - skipping modulation to maintain output - voltage regulation. these two forms of operation are discussed in detail in the light load operation section. note that the converter can also be designed to operate in discontinuous conduction mode at full load if desired. overall, the current - mode regulation system of the adp1621 allows fast transient responses while maintaining a stable output voltage. by selecting the p roper resistor - capacitor network from comp to gnd, the regulator response can be optimized for a wide range of input voltages, output voltages, and load currents. current - sense configurations the adp1621 can sense the current across the on resistance of the mosfet to minimize external component count and improve efficiency by eliminating the power that would be lost in a current - sense resistor. this lossless technique eliminates the need for an expensive current - sense resistor. in the lossless mode config uration, the voltage at the cs pin (or the switch - node voltage at the drain of the mosfet) must not exceed 30 v (see figure 28 ). this technique maximizes efficiency and reduces cost. in practice, when the calculated v sw approach es 30 v, one should build the board and measure the actual v sw before committing to the lossless mode design. because of the parasitic inductance in the diode, output capacitor, and pcb traces, v sw typically has narrow peaks that exceed the theoretical max imum voltage at v sw the sum of v out and the forward - voltage drop of diode d1. if the measured peak voltage exceeds 30 v, or if a more accurate current limit is desired, then the cs pin can be connected to an external current - sense resistor in the source of the mosfet ( figure 29 ). the maximum power output is limited by the selection of the external components. in gate sdsn gnd pin cs pgnd l r s d1 v in v out v sw c o 06090-027 adp1621 figure 28 . cs pin connection for v sw < 30 v, lossless mode (no current - sense resistor needed) in cs sdsn gnd pin gate pgnd l r s d1 v in v out r cs v sw c o 06090-028 adp1621 figure 29 . cs pin connection for v sw > 30 v, resistor sense mode with a current - sense resistor, r cs
data sheet adp1621 rev. b | page 13 of 32 current limit the current limit is achieved by the comp voltage clamp, owing to the current - mode operation of the adp1621. a de tailed explanation of how the current limit is determined can be found in the current limit section of the application information: boost converter section. undervoltage lockout an internal undervolta ge lockout (uvlo) circuit at the in pin holds the gate voltage low when the in voltage is below the uvlo voltage, which is typically 2.5 v. shutdown the adp1621 goes into shutdown approximately 50 s after the sdsn pin is pulled low or left floating. there is an internal 100 k? resistor connected between sdsn and gnd. when the junction temperature of the adp1621 reaches about 150c, the adp1621 goes into thermal shutdown and the gate voltage is pulled low. when the junction temperature drops below about 140 c, the adp1621 resumes normal operation after the soft start sequence. soft start the adp1621 has an internal soft start circuit that ramps the fb regulation voltage from 0 v to 1.215 v in 64 steps over 2048 clock oscillator cycles . this soft start ramp allows the output voltage to slowly rise to the steady - state output voltage, preventing input inrush current at startup. internal shunt regul ators the in and pin pins each have an internal shunt regulator that allows the adp1621 to operate over a wide inp ut voltage range. the shunt regulators limit the voltages at in and pin to about 5.5 v, allowing the use of logic - level mosfets independent of the input and/or output voltage. the shunt regulator voltage can reach 5.7 v at 10 ma. s ee figure 9 for the i - v characteristics of these shunt regulators. the internal power is derived from the in pin, whereas the mosfet gate driver (gate) current comes from the power input, pin. by separating the two inputs, pin can be driven with an ext ernal small - signal npn transistor to limit the power loss in the pin shunt regulator when the input voltage is higher than 5.5 v. see figure 37 for an example. the maximum currents going into pin and in should not exceed 35 ma a nd 25 ma, respectively. setting the oscillat or frequency and synchronization freq uency the free - running oscillator frequency, f osc , is set by a resistor from freq to gnd. a 100 k? resistor sets the typical oscillator frequency to 200 khz, a 65 k? resistor sets it to 325 khz, a 32 k? resistor sets it to 600 khz, and a 10 k? resistor sets it to 1.5 mhz. figur e 30 shows a typical relationship between f osc and r freq . 1600 0 0 200 r freq (k ?) f osc (khz) 1500 1400 1300 1200 1100 1000 900 800 700 600 500 400 300 200 100 20 40 60 80 100 120 140 160 180 06090-029 figure 30 . f osc vs. r freq the switching frequency can be synchronized to an external clock by driving the sdsn pin with that clock signal. the sdsn pin serves the two fu nctions of shutdown control and frequency synchro nization input. if the sdsn input detects a low - to - high transition within 10 s of a high - to - low transition, it resets the oscillator to synchronize to the frequency of the signal at sdsn. the adp1621 only s ynchronizes to frequencies greater than the free - running switching frequency. to ensure proper synchronization operation, set the synchronization frequency, f sync , to 1.2 the free - running frequency, f osc . the switching frequency, f sw , is equal to f sync . a lthough the switching frequency can be synchronized to as high as 1.8 mhz, the peak slope - compensation current decreases at higher f sync . it is recommended that the maximum f sync be less than 1.4 of f osc . the slope - compensation resistor, r s , should be cho sen for the synchronization frequency (see the slope compensation section). for sdsn to detect a high input, the high state must remain high for at least 100 ns.
adp1621 data sheet rev. b | page 14 of 32 application informat ion: boost converter in this section, an an alysis of a boost converter is presented, along with guidelines for component selection. a typical boost - converter application circuit is shown in figure 1 . adi sim p ower design tool the adp 1 621 is supported by adisimpower design tool set. adisimpower is a collection of tools that produce complete power designs optimized for a specific design goal. the tools enable the user to gene rate a full schematic, bill of materials, and calculate performance in minutes. adisimpower can optimize designs for cost, area, efficiency, and parts count while taking into consideration the operating c onditions and limitations of the ic and all real external components. for more information about adisimpower design tools, refer to www.analog.com/adisimpo wer . the tool set is available from this website, and users can also request an unpopulated board through the tool. duty cycle to determine the worst - case inductor current ripple, output voltage ripple, and slope - compensation factor, it is first necessar y to determine the system duty cycle. the duty cycle in continuous conduction mode (ccm) is calculated by the equation d out in d out v v v v v d + ? + = (1) where v out is the desired output voltage, v in is the input voltage, and v d is the forward - voltage drop of the diode. a typical schottky diode has a forward - voltage drop of 0.5 v. the gate minimum on and off times determine the minimum and maximum duty cycles, respectively. the minimum on and off times are typically 180 ns and 190 ns, respectively. the minimum an d maximum duty cycles are given by sw min on sw min on min f t t t d = = , , (2) ) ( 1 1 , , sw min off sw min off max f t t t d ? = ? = (3) where d min is the minimum duty cycle, d max is the maximum duty cycle, t on,min is the minimum on time, t o f f, m i n is the minimum off time, t sw is the switching period, and f sw is the switching frequency. note that when the converter tries to operate at a duty cycle lower than d min , pulse - skipping modulation occur s to maintain the output voltage regulation (see the light load operation section ). setting the output v oltage the output voltage is set through a voltage divider from the output voltage to the fb input. the feedback resistor ratio sets the output voltage of the system. the regulation voltage at fb is 1.215 v. the output voltage is gi ven by (see figure 1 ) ? ? ? ? ? ? + = r2 r1 v out 1 v 215 . 1 (4) the input bias current into fb is 25 na typical, 70 na maximum. for a 0.1% degradation in regulation voltage and with 70 na bias current, r2 must be less than 18 k?, which results in 68 a of divider current. choose the value of r1 to set the output voltage. using higher values for r2 results in reduced output voltage accuracy due to the input bias current at the fb pin, whereas lower values cause increased quiescent current consumption. inductor current rip ple choose a peak - to - peak inductor ripple current between 20% and 40% of the average inductor current. a good starting point for a design is to choose the peak - t o - peak ripple current to be 30% of 1/(1 ? d) times the maximum load current: d i i max load l ? = ? 1 3 . 0 , (5) where i l is the peak - to - peak inductor ripple current, and i load,max is the maximum load current required by the application. inductor selection the in ductor value choice is important because it dictates the inductor current ripple and therefore the voltage ripple at the output. the average inductor current, i l ,ave , is given by d i i load ave l ? = 1 , (6) and the peak - to - peak inductor ripple current is inversely proportional to the inductor value: l f d v i sw in l = ? (7) where f sw is the switching frequency, and l is the inductor value. assuming continuous conduction mode (ccm) operation, the peak inductor current is given by l f d v d i i d i i sw in load l load pk l + ? = ? + ? = 2 1 2 1 , (8) smaller inductor values are typically smaller in size and usually less expensive, but increase the ripple current. larger ripple current also increases the power loss in the inductor core. too large an inductor value results in added expense and may i mpede load transient responses because it reduces the effect of slope compensation.
data sheet adp1621 rev. b | page 15 of 32 assuming the ripple current is 30% of 1/(1 ? d) times the max - imum load current, a reasonable choice for the inductor value is ( ) max load sw in i f d d v l , 3 . 0 1 ? = (9) from this starting point, modify the inductance to obtain the right balance of size, cost, and output voltage ripple while maintaining the induc tor ripple current between 20% and 40% of 1/(1 ? d) times the maximum load current. keep in mind that the inductor saturation current must be greater than the peak inductor current. magnetically shielded inductors are generally recommended, although they c ost slightly more than unshielded inductors. also, losses due to the inductor winding resistance reduce the efficiency of the boost converter. this power loss is given by w load w l r d i p ? ? ? ? ? ? ? = 2 , 1 (10) where p l,w is the power dissipation in the winding of th e inductor, and r w is the winding resistance. input capacitor sele ction the bulk input capacitor provides a low impedance path for the inductor ripple current. capacitor c1 in figure 1 represents a bulk input capacitor. choose a bulk input capacitor whose impedance at the switching frequency is lower than the impedance of the voltage source v in . the preferred bulk input capacitor is a 10 f to 100 f ceramic capacitor because it has low equivalent series resistance (esr) and low impedance. aluminum electrolytic and aluminum polymer capacitors can also be used as the bulk input capacitors. the bulk input capacitor does not need to be placed very close to the in and pin pins. aluminum electrolytic capacitors are the cheapest and ge nerally have high esr values, which increase dramatically at temperatures less than 0c. some aluminum electrolytic capacitors have esr less than 20 m?, but their capacitances are generally greater than 800 f. aluminum polymer capacitors are more expensiv e than the aluminum electrolytic ones, but are generally cheaper than the ceramic capacitors for the same amount of capacitance. polymer capacitors have relatively low esr, with some models having less than 10 m?. regardless of the type of capacitor used, make sure the ripple current rating of the bulk input capacitor, i cin,rms , is greater than 2 3 1 , l rms cin i i ? = (11) where i l is the peak - to - peak inductor ripple current. in addition to the bulk input capacitor, a bypass input capacitor is required. th e function of the bypass capacitor is to locally filter the input voltage to the adp1621 and maintain the input voltage at a steady value during switching transitions. the bypass capacitor is typically a 0.1 f or greater ceramic capacitor and should be pl aced as close as possible to the in and pin pins of the adp1621. capacitors c3 and c4 in figure 1 represent the bypass capacitors. output capacitor sel ection the output capacitor maintains the output voltage and supplies curren t to the load while the external mosfet is on. the value and characteristics of the output capacitor greatly affect the output voltage ripple and stability of the converter. the amount of peak - to - peak output voltage ripple, v out , can be approximated by ? ? ? ? ? ? ? + ? ? 2 1 l load out i d i v ( ) 2 2 2 2 2 1 esl f esr c f sw out sw + + ? ? ? ? ? ? ? ? (12) where i l is the peak - to - peak inductor ripple current, f sw is the switching frequency, c out is the output capacitance, esr is the effective esr of c out , and esl is the effective equivalent series inductance of c out . because the output capacitor is typically greater than 40 f, the esr dominates the output capacitance impedance and thus the output voltage ripple. the use of low esr, ceramic dielectric capacitors is preferred, although aluminum elec trolytic, tantalum, os - con? (from sanyo), and aluminum polymer capacitors can be used. at higher switching frequencies, the esl of the output capacitor may also be a factor in determining the output voltage ripple. multiple capacitors can be connected in p arallel to reduce the effective esr and esl. keep in mind that the capacitance of a given capacitor typically degrades with increased temperature and bias voltage. consult the capacitor manufacturers data sheet when determining the actual capacitance of a capacitor under certain conditions. ensure that the output capacitor ripple current rating, i cout,rms , is greater than d d i i load rms cout ? = 1 , (13) diode selection the diode conducts the inductor current to the output capacitor and load while the mosfet is off. the average diode current is the load current: load ave diode i i = , (14) the rms diode current in continuous conduction mode is given by d d i i load rms diode ? ? = 1 1 , (15) where d is the duty cycle. the power dissipated in the diode is load d diode i v p = (16) where v d is the forward - voltage drop of the diode.
adp1621 data sheet rev. b | page 16 of 32 the total power dissipation determines the diode junction temperature, which is given by ja diode a diode j p t t + = , (17) where t j,diode is the junction temperature, t a is the ambient tem - per ature, and ja is the junction - to - ambient thermal resistance of the diode package. the diode junction temperature must not exceed its maximum rating at the given power dissipation level. for high efficiency, schottky diodes are recommended. the low forwar d - voltage drop of a schottky diode reduces the power losses during the mosfet off time, and the fast switching speed reduces the switching losses during the mosfet transitions. however, for high voltage, high temperature applications where the reverse leak age current of the schottky diode can become significant and degrade efficiency, use an ultrafast - recovery junction diode. make sure that the diode is rated to handle the average output load current. many diode manufacturers derate the current capability o f the diode as a function of the duty cycle. verify that the diode is rated to handle the average output load current with the minimum duty cycle. also, ensure that the peak inductor current is less than the maximum rated current of the diode. mosfet sele ction when turned on, the external n - channel mosfet allows energy to be stored in the magnetic field of the inductor. when the mosfet is turned off, this energy is delivered to the load to boost the output voltage. the choice of the external power mosfet d irectly affects the boost converter performance. choose the mosfet based on the following: threshold voltage (v t ), on resistance (r dson ), maximum voltage and current ratings, and gate charge. the minimum operating voltage of the adp1621 is 2.9 v. choose a mosfet with a v t that is at least 0.3 v less than the minimum input supply voltage at pin used in the application. ensure that the maximum v gs rating of the mosfet is at least a few volts greater than the maximum voltage that is applied to pin. ensure tha t the maximum v ds rating of the mosfet exceeds the maximum v out by at least 5 v to 10 v. depending on parasitics, the mosfet may be exposed to voltage spikes that exceed the sum of v out and the forward - voltage drop of the diode. estimate the rms current in the mosfet under continuous conduction mode by d d i i load rms mosfet ? = 1 , (18) where d is the duty cycle. derate the mosfet current at least 20% to account for inductor ripple and changes in the forward - voltage drop of the diode. the mosfet power dissipati on due to conduction is thus ( ) k r d d i p dson load c + ? ? ? ? ? ? ? = 1 1 2 (19) where p c is the conduction power loss, and r dson is the mosfet on resistance. the variable k is a factor that models the increase of r dson with temperature: ( ) c 25 c / 005 . 0 ? ? ? = j,mosfet t k (20) where t j,mo sfet is the mosfet junction temperature. note that multiple n - channel mosfets can be placed in parallel to reduce the effective r dson . the power dissipation due to switching transition loss is approximated by ( ) ( ) 2 1 sw f r load d out sw f t t d i v v p + ? + = (21) where p sw is the s witching power loss, t r is the mosfet rise time, and t f is the mosfet fall time. the mosfet rise and fall times are functions of both the gate drive circuitry and the mosfet used in the application. the total power dissipation of the mosfet is the sum of the conduction and transition losses: sw c mosfet p p p + = (22) where p mosfet is the total mosfet power dissipation. ensure that the maximum power dissipation is significantly less than the maximum power rating of the mosfet. the total power dissipatio n also determines the mosfet junction temperature, which is given by ja mosfet a mosfet j p t t + = , (23) where t j,mosfet is the junction temperature, t a is the ambient temperature, and ja is the junction - to - ambient thermal resistance of the mosfet package. the m osfet junction temperature must not exceed its maximum rating at the given power dissipation level. if lossless current sensing is not used, there will also be power dissipation in the external current - sense resistor, r cs . the power dissipation, p cs , in th e external resistor due to conduction losses is given by cs load cs r d d i p ? ? ? ? ? ? ? = 2 1 (24) loop compensation the adp1621 uses external components to compensate the regulator loop, allowing optimization of the loop dynamics for a given application. the step - u p converter produces an undesirable right - half plane (rhp) zero in the regulation feedback loop. this rhp zero requires compensating the regulator such that the crossover
data sheet adp1621 rev. b | page 17 of 32 frequency occurs well below the frequency of the rhp zero. the location of the rhp ze ro is determined by the following equation: ( ) l r d f load rhp z ? = 2 1 2 , (25) where f z,rhp is the rhp zero frequency, and r load is the equivalent load resistance or the output voltage divided by the load current. to stabilize the regulator, ensure that the regu lator crossover frequency is less than or equal to one - fifth of the rhp zero frequency and less than or equal to one - fifteenth of the switching frequency. for an initial practical design, choose the crossover frequency f c to be the lower of 15 sw c f f = (26) and 5 , rhp z f c f = (27) where f c is the crossover frequency, and f sw is the switching frequency. the regulator loop gain is ( ) | | 1 | | 1 out cs comp m out fb vl z r n z g d v v a ? = (28) where a vl is the loop gain, v fb is the feedback regulation voltage (typically 1. 215 v), v out is the regulated output voltage, d is the duty cycle, g m is the error amplifier transconductance gain (typically 300 s), z comp is the impedance of the rc network from comp to gnd, n is the current - sense amplifier gain (typically 9.5), r cs is the current - sense resistance, and z out is the impedance of the load and output capacitor. in the case of lossless current sensing, as shown in figure 28 , r cs is equal to the on resistance, r dson , of the external power mosfet. ot herwise, r cs represents the external current - sense resistor, as shown in figure 29. to determine the crossover frequency, it is important to note that at that frequency the compensation impedance, z comp , is dominated by resisto r r comp , and the output impedance, z out , is dominated by the impedance of the output capacitor, c out . when solving for the crossover frequency, the equation is simplified to = | | vl a ( ) 1 2 1 1 1 = ? out c cs comp m out fb c f r n r g d v v (29) where f c is the crossover f requency, r comp is the compensation resistor, and c out is the output capacitance. solving for r comp gives ( ) m fb out cs out c comp g d v v r n c f r ? = 1 2 (30) once the compensation resistor, r comp , is known, set the zero formed by the resistor and compensation capacitor, c comp , to one - fourth of the crossover frequency, or comp c comp r f c = 2 (31) capacitor c2 is chosen to cancel the zero introduced by the output capacitance esr. thus, c2 should be set to (see figure 31) comp out r c esr c = 2 (32 ) where esr represents the esr of c out . for low esr output capacitors, such as ceramic capacitors, c2 is small, generally in the range of 10 pf to 400 pf. because of the parasitic inductance, resistance, and capacitance of the pcb layout, the r comp , c com p , and c2 values might need to be adjusted by observing the load transient response of the adp1621 to establish a stable operating system and achieve optimal transient performance. for most applications, r comp is in the range of 5 k ? to 100 k?, and c comp is in the range of 100 pf to 30 nf. comp c comp r comp c2 ref g m 2 3 06090-030 figure 31 . compensation components slope compensation the adp1621 includes a circuit that allows adjustable slope compensation. slope compensation is required by curre nt - mode regulators to stabilize the current - control loop when operating in continuous conduction and the switching duty cycle is greater than 50%. slope compensation is achieved by internally forcing a ramping current source out of the cs current - sense pi n. by placing a resistor between the cs pin and the current sensing device (the drain of the external mosfet in the case of lossless current sensing or the source of the mosfet if a current - sense resistor is used), a voltage is developed across the resisto r that is proportional to the slope - compensation current. to ensure stability of the current - mode control loop, use a compensation voltage slope that is equal to or greater than one - half of the current - sense representation of the inductor current downslop e. therefore, it follows that l v v v r f t f i r in d out cs sw min off, sw sc,pk s ? + > ? 1 2 (33) where r s is the slope - compensation resistor, i sc,pk is the peak slope - compensation current, f sw is the switching frequency, r cs is the current - sense resistor, v out is the regulated output voltage, v d is the forward - voltage drop of the diode, v in is the input voltage, t o f f, m i n is the minimum off time, and l is the power - stage inductor. in the case of lossless current sensing, r cs is equal to the on resistance,
adp1621 data sheet rev. b | page 18 of 32 r dson , of the external power mosfet. ot herwise, r cs represents the external current - sense resistor. solving for r s gives the slope - compensation criterion: ( ) ( ) l f i f t v v v r r sw pk sc sw min off in d out cs s ? ? + > , , 2 1 (34) keep in mind that the above inequality is a function of both adp1621 parameters and off - chip components, the values of which vary from part to part and with temperature. select r s to ensure current - loop stability for all possible variations. after accounting for parameter variations, use values of r s that are as close to the calculated limit as possible because excessive slope compensation reduces the benefits of current - mode control and increases the softness of the current limit, as discussed in the current limit section. given a typical peak slope - compensation current of 70 a, r s should not exceed 1.6 k? because the voltage at the cs pin is typically clamped at 116 mv. it is also recom - mended that r s be greater than 20 ?. if the calculated r s is greater than 1.6 k?, the parameters in equation 34, such as r cs , f sw , and l, can be ad justed such that r s is less than 1.6 k?. in conclusion, the value of r s should be 20 ? r s 1.6 k?. current limit the current limit in the adp1621 limits the peak inductor current and is achieved by the comp voltage clamp. the peak inductor current, i l, pk , is given by cs sw min off s pk sc zct comp clamp comp pk l r f t d r i n v v i ? ? ? = , , , , , 1 (35) where v comp,clamp is the comp clamp voltage (typically 2.0 v), v comp,zct is the comp zero - current threshold (typically 1.0 v), n is the current - sense amplifier gain (typically 9.5), i sc,pk is the peak slope - com pensation current (typically 70 a), r s is the slope - compensation resistor, d is the duty cycle, f sw is the switching frequency, t o f f, m i n is the minimum off time (typically 190 ns), and r cs is the current - sense resistor. in the case of lossless current sen sing, r cs is equal to the on resistance, r dson , of the external power mosfet. otherwise, r cs represents the external current - sense resistor. the current limit in the adp1621 is a soft current limit. when the inductor current reaches the i l,pk limit give n in equation 35, the duty cycle decreases, and the output voltage drops below the desired voltage. the i l,pk limit in equation 35 then increases in response to the smaller duty cycle, d. the larger the slope - compensation resistor, r s , the larger the effec t on i l,pk for an incremental decrease in d. this behavior results in a soft current limit for the adp1621. use values of r s that are as close as possible to the calculated limit derived from equation 34. if high - precision current limiting is required, c onsider inserting a fuse in series with the inductor. also, keep in mind that the current limit is a function of both adp1621 parameters and off - chip components, the values of which vary from part to part and with temperature. if lossless current sensing i s used, consider that the on resistance of a mosfet typically increases with increasing junction temperature. the peak inductor current limit also limits the maximum load current at a given output voltage. the maximum load current, assuming ccm operation, is given by ( ) ? = d i max load 1 , ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? l f d v r f t d r i n v v sw in cs sw min off s pk sc zct comp clamp comp 2 1 , , , , (36) if the load current exceeds i load,max , the output voltage drop s below the desired voltage. light load operation discontinuous conduction mode with light loads, the average inductor curren t is small, and, depending on the converter design, the instantaneous inductor current may reach 0 during the time when the mosfet is off. this mode of operation is termed discontinuous conduction mode. the condition for entering discontinuous conduction m ode in a boost converter is ( ) sw in load f l d d v i ? < 2 1 (37) when the instantaneous inductor current reaches 0 during the cycle, the inductor ceases to be a current source, and ringing can be observed in the waveforms of the mosfet drain voltage and the induc tor current. the frequency of the ringing is the resonant frequency of the inductor and the total capacitance from the sw node to gnd, which includes the capacitances of the mosfet and diode, and any parasitic capacitances from the pcb. while adding a resi stive element, such as a snubber, to the system further dampens the resonance, it also decreases the efficiency of the regulator. pulse - skipping modulation the adp1621 features circuitry that improves the converter efficiency and minimizes power consumpti on with no load or very light loads. when the comp voltage drops below v c o m p, z c t (typically 1.0 v), which can occur at sufficiently light loads, the mosfet is powered off until the fb voltage drops below 1.215 v. then, the error amplifier drives the comp v oltage higher, and the converter resumes switching when the comp voltage rises above the v comp,zct voltage. while the mosfet is powered off, the output capacitor supplies current to the load. with light loads, the comp voltage hovers around 1.0 v, and sho rt periods of switching are followed by long periods of the mosfet being powered off. this pulse - skipping modulation operation improves converter efficiency by reducing the number of switching cycles and therefore reducing the gate drive current and the sw itching transition power loss.
data sheet adp1621 rev. b | page 19 of 32 given the minimum on time of the adp1621, pulse - skipping modulation is also a requirement to maintain output voltage regulation with light loads. during the short switching periods of pulse - skipping modulation, the mosfet is turned on for the minimum on time each cycle, storing just enough energy in the inductor to charge the output capacitor. during the long period when the mosfet is off, no current flows through the inductor, and the light load current is supplied by the ou tput capacitor. recommended componen t manufacturers table 5 . vendor components avx corporation capacitors central semiconductor corp. diodes coilcraft, inc. inductors diodes, inc. diodes international rectifier diodes, mosfe ts murata manufacturing co., ltd. capacitors, inductors on semiconductor diodes, mosfets rubycon corporation capacitors sanyo capacitors sumida inductors taiyo yuden, inc. capacitors, inductors toko america, inc. inductors united chemi - con, inc. ca pacitors vishay siliconix diodes, mosfets, resistors, capacitors
adp1621 data sheet rev. b | page 20 of 32 layout consideration s layout is important for all switching regulators, but is par - ticularly important for regulators with high switching frequencies. to achieve high efficiency, good r egulation, and stability, a well - designed printed circuit board layout is required. a sample pcb layout for the standard boost converter circuit shown in figure 33 is given in figure 32. follow these guidelines when designing printed circuit boards: ? keep the low esr bypass input capacitor of 0.1 f or higher close to in/pin and gnd. ? keep the high current path from bulk input capacitor c1 through inductor l1 and mosfet m1 to pgnd as short as possible. ? keep the high current path from bulk input capacitor c1 through inductor l1, diode d1, and output capacitor c out to pgnd as short as possible. place c out as close to pgnd as possible to reduce ground bouncing. ? keep high current traces as short and wide as possible to minimize parasitic series inductance, which causes spiking and electromagnetic interference (emi). ? to minimize switching noise, the drain of the power mosfet should be placed very close to the inductor, and the source of the mosfet (or the bott om side of the sense resistor) should be connected directly to the power gnd plane. use wide copper traces on the drain and on the source of the mosfet to minimize parasitic inductance and resistance. parasitic inductance can lead to excessive ringing duri ng switching transitions, and parasitic resistance reduces the converter efficiency. make sure that the mosfet selected is capable of handling the total power loss (conduction plus transition losses) in the application circuit. ? avoid routing high impedanc e traces near any node con - nected to the switch node (the mosfet drain) or near inductor l1 to prevent radiated switching - noise injection. ? add an extra copper plane at the connection of the mosfet drain and the anode of the diode to help dissipate the hea t generated by losses in those components. ? avoid ground loops by having one central ground node on the pcb. if this is impractical, place the power ground with high current levels physically closer to the pcb ground terminal. the analog, low current - level ground should be placed farther from the pcb ground terminal. ? minimize the length of the pcb trace between the gate pin and the mosfet gate. the parasitic inductance in this pcb trace can give rise to excessive voltage ringing at the mosfet gate and drain , as well as the regulator output. it is recommended to add 5 ? of resistance for every inch of pcb trace. this help s to reduce the overshoot and ringing at the drain and the output. however, this added resistance increases the rise and fall times of the m osfet; thus, the switching loss in the mosfet is increased. ? place the feedback resistors as close to fb as possible to prevent high frequency switching - noise injection. ? place the top of the upper feedback resistor, r1, as close as possible to the top of c out for optimum output voltage sensing. ? if a current - sense resistor is connected between the source of the mosfet and pgnd, ensure that the capacitance from cs to pgnd is minimized. ? place the compensation components as close as possible t o c o m p. v in v out c out1 c out2 vias to gnd plane vias to 2nd layer remote output sensing c out3 l1 gnd c1 gnd sdsn adp1621 c3 c2 r1 r2 c4 r freq r comp r s c comp gate d1 m1 06090-031 figu re 32 . pcb layout of the circuit shown in figure 33 (2- layer pcb)
data sheet adp1621 rev. b | page 21 of 32 efficiency considera tions the efficiency, , of a dc/dc converter is given by % 100 = in out p p (38) where p out is the output power, and p in is the input power to the converter. while switching regulators are ideally lossless converters of power, the nonideal characteristics of regulator components degrade the efficiency of the regulator. the primary sources of power dissipation in the regulator include ? the power dissipation in the external power mosfet due to conduction and switching losses. sw c mosfet p p p + = (39) + ? ? ? ? ? ? + ? ? ? ? ? ? ? = ) 1 ( 1 k r d d i dson load ? ? ? ? ? ? ? ? ? ? ? ? + ? + 2 ) ( 1 ) ( sw f r load d out f t t d i v v ? the power dissipation in the external current - sense resistor if lossless current sensing is not used. cs load cs r d d i p ? ? ? ? ? ? ? = 2 1 (40) ? the power dissipation in the external diode. load d diode i v p = (41) ? the power dissipation in the winding resistance of the power stage inductor. w load w l r d i p ? ? ? ? ? ? ? = 2 , 1 (42) ? the supply current to the adp1621 ic, which includes the quiescent current and the gate driver charging current. the power dissipation due to gate charging loss is approximated by sw g pin g f q v p = (43) where p g is the gate charging power loss, v pin is the voltage at the pin pin, q g is the mosfet total gate charge, and f sw is the converter switching frequency. therefore, the total power dissipation in the ic itself is given by ( ) q in g ic i v p p + = (44) ( ) ( ) q in sw g pin i v f q v + = where p ic is the total power dissipated in the ic, i q is the quiescent current, and v in is the voltage at the in pin. the secondary sources of power dissipation in the regulator include ? the power dissipation in the esr of the input and output capacitors. ? inductor core losses due to hysteresis and eddy currents.
adp1621 data sheet rev. b | page 22 of 32 examples of applicat ion circuits standard boost conve rter design example the example covered here is for the adp1621 configured as a standard boost converter, as shown in figure 33 , where lossless current sensing is employed. the design parameters are v in = 3.3 v, v out = 5 v, and a maximum load current of 1 a. to begin this design, a switching frequency of 600 khz is chosen (by setting r freq to 32 k?, see figure 30 ) so that a small inductor and small output capacitors can be used. the duty cycle is cal - culated from equation 1 to be 0.4, given a forward - voltage drop of 0.5 v for the schottky diode. the feedback resi stors are calculated to be r1 = 35.7 k? and r2 = 11.5 k? from equation 4. assuming that the inductor ripple is 30% of 1/(1 ? d) times the maximum load current, the inductor size is calculated to be about 4.4 h, according to equation 9. the small, magnet ically shielded 4.7 h toko fdv0630 - 4r7m inductor is selected. because ceramic capacitors have very low esr (a few milliohms), a 47 f/6.3 v murata grm31cr60j476m ceramic capacitor is chosen for the input capacitor. the output voltage ripple for a given c out , esr, and esl can be found by solving equation 12. by choosing an output voltage ripple equal to 1% of the output voltage, equation 12 yields that the minimum c out required is 100 f and the maximum esr required is 25 m ?. other com - binations of capacitance and esr are possible by choosing a much larger c out and a larger esr. in this case, a small 1 f ceramic capacitor and two 150 f sanyo poscap? capacitors are selected. the low esr ceramic capacitor helps to suppress t he high frequency overshoot at the output. poscap has low esr and high capacitance in a relatively small package. ceramic capacitors can also be used. generally, bigger ceramic capacitors are more expensive. the next step is to choose a schottky diode. th e average and rms diode currents are calculated to be 1.0 a and 1.3 a, respectively, using equations 14 and 15. a vishay ssa33l schottky diode meets the current and thermal requirements and is an excellent choice. the power mosfet must be chosen based on threshold voltage (v t ), on resistance (r dson ), maximum voltage and current ratings, and gate charge. the rms current through the mosfet is given by equation 18 as 1.1 a. the vishay si7882dp is a 20 v n - channel power mosfet that meets the current and therm al requirements. it comes in a powerpak? package and offers low r dson and gate charge. at v gs = 2.5 v, the on resistance, r dson , is 8 m ?. the loop - compensation components are chosen to be r comp = 9.1 k? and c comp = 1.7 nf from equations 30 and 31, respectively. a roll - off capacitor of c2 = 120 pf is also added. the slope - compensation resistor is set to be r s = 80 ? from equation 34. las tly, given the chosen components, the peak inductor current as set by the current limit circuitry is given by equation 35 as i l,pk = 12 a. thus, the maximum load current, assuming ccm operation, is given by equation 36 as i load,max = 8 a, which is safely above the 1.0 a load current requirement f or this design example. n ote that the current limit is a strong function of r cs , which can vary part to part and with temperature. in addition, note that r cs can be implemented with an external current - sense resist or or with the r dson of a mosfet. variations in r cs and the other parameters in equations 35 and 36 must be taken into account if precise current limiting is necessary. due to the parasitic resistance of pcb traces, r s might need to be adjusted on the actu al circuit board to achieve the desired current limit. keep in mind that r s must be less than 1.6 k ?. using a mosfet with a different r dson or adjusting r cs can also set the current limit to the desired level. adp1621 in gate pgnd agnd fb sdsn comp freq gnd pin cs r1 35.7k? 1% r2 11.5k? 1% c1 47f 6.3v l1 4.7h m1 c comp 1.8nf c out1 1f 10v f osc = 600khz c1 = murata grm31cr60j476m c out3 = sanyo poscap 6tpe150m l1 = toko fdv0630-4r7m m1 = vishay si7882dp d1 = vishay ssa33l r s 80? c out2 10f 10v r freq 31.6k? 1% c out3 150f 6.3v 2 d1 c3 1f 10v c4 0.1f 10v c2 120pf r comp 9.09k? v out = 5v 1a v in = 3.3v 06090-032 figure 33 . typical boost converter application circuit
data sheet adp1621 rev. b | page 23 of 32 bootstrapped boost c onverter the inputs of the adp1621 can b e driven from the step - up converter output voltage to improve efficiency for low input voltages. for low input voltages, bootstrapped operation improves efficiency with heavy loads by increasing the available gate drive voltage, thus reducing the on resist ance of the mosfet. however, because the internal circuitry is driven from in, the adp1621 quiescent current and gate drive current supplied from the input increases due to the step - up ratio and the conversion efficiency loss. the circuit shown in figure 1 shows a bootstrapped boost con - verter, where v in = 3.3 v and v out = 5 v. to ensure that the circuit starts, make sure that the input voltage minus the forward - voltage drop of the diode is greater than the uvlo voltage and the g ate threshold voltage of the mofset. in this example, the mosfet has a gate threshold voltage of 2.5 v. the regulator shown in figure 1 is very similar to that shown in figure 33 , which is a standard boost without bootstrapping. because the same mosfet and inductor are used in both circuits and the input and output conditions are the same, the compensation components remain unchanged. figure 34 shows a bootstrapped applicat ion circuit for output voltages greater than 5.5 v. in this case, the output is 12 v. notice that a resistor, r3, of 700 ? is placed between v out and the in and pin pins to limit the input currents because the in and pin pins are regulated to 5.5 v. a diode, d2, is placed between v in and the in/pin pins to supply the necessary quiescent current to start the adp1621. once the adp1621 starts and the output voltage reaches 12 v, the quiescent current stops flowing through d2 and is supplied by the output. keep in mind that the dynamic supply current to pin increases as the switching fre - quency increases because more gate drive i s needed for a higher switching frequency. therefore, r3 needs to be set appropriately. the pin supply current can be approximated by g sw pin q f i = (45) where i pin is the pin supply current, f sw is the switching frequency, and q g is the gate char ge of a particular mosfet. an alternative implementation to figure 34 is shown in figure 35, where an npn transistor is used to supply the necessary current to the input pin at various loads, but the gate drive voltage is limited to approximately 4.8 v (one diode drop below the voltage at in). signal diodes d2 and d3 help to provide the necessary quiescent current to start the adp1621. once the adp1621 starts, the current stops flowing through these tw o diodes because the voltages at pin and in are approximately 4.8 v and 5.5 v, respectively. one advantage of this technique is that q1 provides enough current to the gate driver at any switching frequency with a wide range of mosfets that have different gate charge specifications. notice that the output capacitor, c out2 in figure 34 and figure 35, is a large aluminum electrolytic capacitor, both in physical size and capacitance. such capacitors are very cheap relative to ceramic capacitors (such as sanyo poscap) or aluminum polymer capacitors. the adp1621 can work with a wide range of capacitor types.
adp1621 data sheet rev. b | page 24 of 32 adp1621 in gate pgnd agnd fb sdsn comp freq gnd pin cs r1 88.7k? 1% r2 10k? 1% c1 47f 6.3v l1 10h m1 c comp 330pf c out1 10f 16v 2 f osc = 600khz c1 = murata grm31cr60j476m c out2 = rubycon 25zl330m8x16 l1 = coilcraft mss1260-103ml m1 = irf7470 d1 = vishay ssc53l d2 = signal diode r s 200? r3 700? r freq 31.6k? 1% c out2 330f 25v 2 v out = 12v 1a d1 d2 c3 1f 10v c4 0.1f 10v c2 220pf r comp 51.5k? v in = 3.3v 06090-033 figure 34 . bootstrapped application circuit for v out > 5.5 v adp1621 in gate pgnd agnd fb sdsn comp freq gnd pin cs r1 88.7k? 1% r2 10k? 1% c1 47f 6.3v l1 10h m1 c comp 330pf c out1 10f 16v 2 f osc = 600khz c1 = murata grm31cr60j476m c out2 = rubycon 25zl330m8x16 l1 = coilcraft mss1260-103ml q1 = signal npn transistor m1 = irf7470 d1 = vishay ssc53l d2, d3 = signal diode r s 200? r3 1.5k? r freq 31.6k? 1% c out2 330f 25v 2 v out = 12v 1a d1 d2 q1 c3 1f 10v c4 0.1f 10v c2 220pf r comp 51.5k? d3 v in = 3.3v 06090-034 figure 35 . bootstrapped application circuit for v out > 5.5 v
data sheet adp1621 rev. b | page 25 of 32 low input and high output boost converter figure 36 shows a typical application boost converter circuit that operates at a switching frequency of 20 0 khz with v in = 5 v and v out = 30 v with a 1 a load. the duty cycle for this circuit is about 83%. a higher switching frequency can be selected, but the switching power loss in the mosfet increases and a bigger mosfet is needed. for switch - node voltages g reater than 30 v, a sense resistor, r cs , is needed because the absolute maximum voltage at cs is 33 v. high input voltage boost converter circuit input voltages higher than 5.5 v are possible with the addition of a resistor and an npn transistor , as shown in figure 37 , or just with a single resistor , as shown in figure 38 . when there is a wide input voltage range, it is sometimes desirable to use the pass npn transistor , as shown in figure 37 . if the input voltage range is narrow, a single resistor connecting to the in and pin pins is sufficient, as shown in figure 38 . in figure 37 , resistor r3 limits the current going into in, and there is power loss in this resistor. the voltages at in and pin are both clamped to about 5.5 v, which can rise to as high as 5.9 v when the shunt current is 30 ma. r efer to figure 9 for the i - v characteristics of the shunt regulators. ensure that resistor r3 is physically large enough to handle the power dissipation. for switch - node voltages higher than 30 v, a current - sense resistor is needed and the cs pin senses the voltage across the sense resistor. adp1621 pin gate cs agnd pgnd sdsn comp freq gnd in fb r1 115k? 1% r2 4.87k? 1% c1 47f 6.3v 2 l1 7.8h m1 c comp 20pf f osc = 200khz c1 = murata grm31cr60j476m c out1 = murata grm31cr72a10 c out2 = murata grm55er71h475k c out3 = rubycon 50zl330m10x23 m1 = vishay sud50n06-07l d1 = irf 15tq060 l1 = coilcraft do501dh-782ml r s 909? r cs 3m? r freq 100k? 1% d1 c3 1f 10v c4 0.1f 10v c2 120pf r comp 1.6m? v in = 5v c out1 1f 100v c out2 4.7f 50v c out3 330f 50v 2 v out = 30v 1a 06090-035 figure 36 . low input , high output boost converter adp1621 pin gate cs agnd pgnd sdsn comp freq gnd in fb r1 115k? 1% r3 700? r2 4.87k? 1% c1 22f 16v 2 l1 8.2h m1 c comp 220pf f osc = 560khz c1 = murata grm32er61c226k c out1 = murata grm31cr72a105k c out2 = murata grm55er71h475k c out3 = rubycon 50zl220m10x23 m1 = irf7470 q1 = signal npn transistor d1 = mbrb7h50 l1 = coilcraft mss1260-822ml r s 402? r cs 3m? r freq 34.8k? d1 q1 c4 0.1f 10v c3 1f 10v c2 120pf r comp 2m? v in = 8v to 15v c out1 1f 100v c out2 4.7f 50v c out3 330f 50v 2 v out = 30v 1a 06090-036 figure 37 . high input voltage and high output voltage converter
adp1621 data sheet rev. b | page 26 of 32 adp1621 pin gate cs agnd pgnd sdsn comp freq gnd in fb r1 324k? 1% r2 10.2k? 1% r3 649? c1 22f 16v 2 l1 15h m1 c comp 18pf f osc = 560khz c1 = murata grm32er61c226k c out1 = murata grm31cr72a105k c out2 = murata grm55er71h475k c out3 = rubycon 63zl220m10x23 m1 = vishay si7478dp d1 = mbrb7h50 l1 = coilcraft mss1278-153ml r s 442? r cs 0.01? r freq 34.8? d1 c3 1f 10v c4 0.1f 10v c2 120pf r comp 2m? v in = 12v c out1 1f 100v c out2 4.7f 50v c out3 220f 63v 2 v out = 40v 1a 06090-037 figure 38 . high input voltage and high output voltage converter
data sheet adp1621 rev. b | page 27 of 32 sepi c converter circuit a single - ended primary inductance converter (sepic) topology is shown in figure 39 . this topology is useful for an unregulated input voltage, where the regulated output voltage falls within the input voltage range. the input and output are dc - isolated by a coupling capacitor, c5. l1 and l2 are coupled inductors with a 1:1 turn ratio, which saves space on the pcb. in steady state, the average voltage across c5 is the input voltage. when the mosfet turns on and the diode turns off, the input voltage provides energy to l1, and c5 provides energy to l2. the output capacitor, c out , supplies the load current during this time. when the mosfet turns off and the diode turns on, the energy in l1 and l2 is released to ch arge the output capacitor, c out , and the coupling capacitor, c5, as well as to supply current to the load. low voltage power - input circuit the adp1621 can be configured to run from a low voltage (as low as 1 v) power input. the power source generally nee ds to have a high current capability, such as a fuel cell. figure 40 illustrates such an application, where the voltage of the power input is 1 v and the voltage of the chip supply to the in and pin pins is provided by an auxili ary low power source. adp1621 in gate pgnd agnd fb sdsn comp freq gnd pin cs r1 17.4k? 1% r2 10k? 1% c1 22f 10v 2 c5 10f 10v x5r l2 2.4h l1 2.4h m1 c comp 1.2nf f osc = 325khz c1 = murata grm332er61a226k c out2 = sanyo poscap 6tpe150mi c5 = murata grm21br61a106k l1, l2 = coupled inductors, 1:1 ratio, bh electronics bh510-1006 m1 = vishay si7882dp d1 = vishay ssc53l r s 80? c out1 1f 10v r freq 65k? c out2 150f 6.3v 3 v out = 3.3v 2a v in = 3v to 5.5v d1 c3 1f 10v c4 0.1f 10v c2 33pf r comp 26k? 06090-038 figure 39 . a sepic dc/dc converter adp1621 in gate pgnd agnd fb sdsn comp freq gnd pin cs r1 35.7k? 1% r2 11.5k? 1% c1 100f x5r 6.3v l1 2.2h m1 c comp 56nf c out1 1f 10v f osc = 600khz c1 = murata grm32er60j107me20 c out2 = murata grm21br60j106k c out3 = sanyo poscap 6tpe150mi m1 = vishay si7882dp d1 = mbrd835l l1 = toko fdv0630-2r2m r s 249? c out2 10f 6.3v r freq 31.6k? 1% c out3 150f 6.3v 2 v out = 5v 1a v in = 1v v cc = 2.9v to 5.5v d1 c3 1f 10v c4 0.1f 10v c2 260pf r comp 9.4k? 06090-039 figure 40 . low voltage power - input application circuit
adp1621 data sheet rev. b | page 28 of 32 led driver applicati on circuits the adp1621 can be used as an led driver. two led app lication circuits are shown in figure 41 and figure 42 , where each circuit is driving 20 white leds in series. each white led has a typical current of 150 ma at a typical forward voltage of 4.0 v, wit h a maximum voltage of 4.5 v over the temperature range of ?40c to +125c . two methods for dimming the brightness of the leds are shown in figure 41 and figure 42 . in fig ure 41 , a pwm signal is fed to the sdsn pin to turn the adp1621 controller on and off. as a result, the led current is turned on and off, and the average led current is dependent on the pwm duty cycle. the advantage of this method is that no current flows through the leds during the pwm off cycle. in addition, when the adp1621 is on, the forward current through the leds is constant, which guarantees constant color emission across the entire dimming range. because the soft start period is fixed at 2048 osci llator cycles, the pwm frequency range is limited. as shown in figure 41 , because the natural switching frequency chosen is 400 khz, the useful pwm frequency range is 90 hz to 195 hz. however, when driving fewer leds, the adp16 21 can be set to run at a faster frequency, increasing the maximum pwm frequency. the pwm duty cycle can be between 5% and 95%. a higher pwm duty cycle produces a higher average led current. another method for driving the leds is shown in figure 42, where the pwm signal is filtered by an rc low - pass filter and is fed to the fb node. the effective fb voltage at the bottom of the led string is modulated in an analog manner by the pwm duty cycle. thus, the average current through th e leds is modulated accordingly. unlike the case depicted in figure 41 , a higher duty cycle produces a lower average led current using the filtered pwm scheme in figure 42 . the advantage of this circu it is that the pwm frequency can be in the range between 90 hz and 100 khz, and the duty cycle can be between 5% and 95%. the disadvantage of this method is that the forward current through the leds is directly modified to control the brightness of the led s. because the wavelength of the light emitted from an led is a weak function of its forward current, perfect color purity across the entire dimming range cannot be guaranteed. if pcb space is a constraint, smaller inductors can be selected for the circui ts shown in figure 41 and figure 42 . for example, a 4.7 h inductor can be used, and a 200 khz switching fre - quency can be selected. however, with this small inductor, the system operates in dcm, whic h is slightly less efficient than operating in ccm.
data sheet adp1621 rev. b | page 29 of 32 adp1621 in cs fb agnd pgnd sdsn comp freq gnd pin pwm gate r1 8 ? 1/4w 150ma 20 leds r b 800 ? c1 2.2f 25v l1 33h m1 100v c comp 390nf f osc = 400khz c1 = murata grm31mr71e225k c out = murata grm31cr72a105k l1 = coilcraft mss1038-333nl m1 = vishay si4482dy d1 = irf 10mq100 r s 800 ? c out 1f 100v 3 r freq 50k? 1% v out v in = 10v to 16 v d1 100v c3 0.1f c4 0.1f c2 18pf r comp 101k ? r cs 3m ? 06090-040 figure 41. 20-series led driver with pwm at sdsn adp1621 in cs fb agnd pgnd sdsn comp freq gnd pin pwm = 0v to 4v gate r1 8 ? 1/4w r5 18k ? 150ma 20 leds r b 800 ? c1 2.2f 25v l1 33h m1 100v c5 0.1f 6.3v c comp 390nf f osc = 400khz c1 = murata grm31mr71e225k c out = murata grm31cr72a105k l1 = coilcraft mss1038-333nl m1 = vishay si4482dy d1 = irf 10mq100 r s 800 ? r2 10k ? r3 22.9k ? r4 10k ? c out 1f 100v 3 r freq 50k? 1% v out v in = 10v to 16 v d1 100v c3 0.1f c4 0.1f c2 10pf r comp 101k ? r cs 3m 06090-041 figure 42. 20-series led driver with filtered pwm
adp1621 data sheet rev. b | page 30 of 32 related parts table 6. part number description comments adp1612 current-mode pwm step-up controller 1.4 a, internal fet r dson is 130 m nominal, v in = 1.8 v to 5.5 v, v outmax is 20 v adp1613 current-mode pwm step-up controller 2.0 a, internal fet r dson is 130 m nominal, v in = 2.5 v to 5.5 v, v outmax is 20 v adp1614 current-mode pwm step-up controller 4.0 a, internal fet r dson is 50 m nominal, v in = 2.5 v to 5.5 v, v outmax is 20 v
data sheet adp1621 rev. b | page 31 of 32 outline dimensions compliant to jedec sta ndards mo-187-ba 091709-a 6 0 0.70 0.55 0.40 5 1 0 1 6 0.50 bsc 0.30 0.15 1. 10 max 3.10 3.00 2.90 copla narit y 0.10 0.23 0. 13 3.10 3.00 2.90 5.15 4.90 4.65 pin 1 identifier 15 max 0.95 0.85 0.75 0.15 0.05 figure 43 . 10 - lead mini small outline package [msop] (rm - 10) dimensions shown in millimeters ordering guide model 1 temperature range package description package option ordering quantity branding adp1621armz -r7 ?40c to +125c 10- lead mini small outline package [msop] rm - 10 1,000 l3m adp1621 - eval evaluation board 1 1 z = rohs compliant part.
adp1621 data sheet rev. b | page 32 of 32 notes ? 2006 C 2012 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d06090 - 0 - 6/12(b)

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